Some musings on multi-channel ADC choices


It is rather clear that future belongs to digital sound. However, producing sound by exclusively digital means is a rather boring occupation; wood and brass musical instruments are way more fun. Thus, at some stage groovy mechanical vibes must be converted into a bit stream. Even more so, conversion must be done on multiple channels simultaneously – a channel for each vibrating thingy (be it a guitar string or a vocal fold) is desirable.

Fortunately enough, the market is spoiled for choice of multi-channel ADCs. However, some important caveats exist, regarding the digitization methods involved.

Dedicated “Hi-Fi Audio” converters

Almost every mixed-signal IC manufacturer have those lurking around the beginning of their ADC chip range. Their “paper” stats are rather invariable among manufacturers: 2 – 8 channels, 24 bits of resolution, 200+ kSps sampling rates and sometimes added goodies like on-chip PGAs and programmable filters. I, being a control engineer by education, frown upon those.

Chips, falling into this category, commonly exhibit two rather annoying flaws:

  1. Their analog inputs are most often single ended or pseudo-differential. I stand to claim that nothing good can come out of single-ended transmission lines, even at audio frequencies. For me, only true differential signaling all the way down is acceptable, especially when sensors (read, sound pickups) are concerned.
  2. They rely on delta-sigma modulation for actual digitization process.

Of course, there’s nothing wrong with delta-sigma modulation per se, rather the opposite is true: the technique can be considered a work of genius (and, as is the case with many such important inventions, it was primarily developed at Bell Labs during the golden age of that venerable organization). Yet, while it shines in digital signal amplification and reproduction, it’s use in audio signal acquisition appears to serve as nothing more but excuse for marketing gimmick called “24 bits per sample”.

Delta-sigma modulation is most closely related to frequency modulation used in FM radio broadcasting (in fact, one of the implementation techniques for DS modulator involves using analog FM modulator as its primary building block). Within the DS modulator, the incoming signal is converted into a high, varying frequency (50x the sampling rate is not uncommon) bit stream, which is then digitally demodulated into a high resolution digital estimate of the input signal. Estimated signal is fed back to the DS modulator itself (DS bit stream is generated as a difference between this estimate and actual incoming signal, thus “delta” part of the modulation) and, as a side effect, emitted to the digital output channel in a form of useful, high resolution sample stream.

At this stage, the problem with DS converters should be apparent: their output corresponds not to some momentary value present at the analog input, but to dynamic estimate of this value, produced by a high-order (8th order and above are rather common), specialized topology digital filter.

Now, anybody with the exposure to dynamic system theory may remember that behavior of dynamic systems above 2nd order can not be predicted in closed form. This basically means, that most of the time, DS ADC will be able to precisely guess the value at the analog input. Yet, when facing waveforms, unforeseen or neglected by its designers (and it is outright impossible to optimize high order filters for every possible waveform, so various “describing function” techniques are used to target certain “use cases” during the design process), DS ADC will necessarily have a voice of its own, which may be pleasing or not so much, but in no case welcome at such an early stage of sound processing and delivery pipeline.

Communication and industrial ADCs: the hardcore engineer’s way

So, after a proper thrashing I gave to Delta-Sigma ADCs in the previous part, one obvious question remains: what are the alternatives? This question is even more interesting if one recollects that really good DS ADCs are very complex beasts when internal electronics is concerned, and thus draw a lot of power (which may not be available, due to power source or cooling concerns; I shall return to this point later).

First, we need to address (lightly) an important philosophical concern: how at all some physical value can be “measured” at all? What does this magical act of measurement means and how can it be achieved?

It appears, that the only way to measure something, is to compare that something to something else, of known properties. One can compare her or his height to a refrigerator in the kitchen, to achieve a pretty good estimate of the actual height value. In case of ADCs, we are comparing the input voltage to a precision voltage reference of known value, normally set at the exact middle of the ADC’s useful measurement range (all ADCs do this, even DS ones).

Unfortunately, comparing the input to a single reference gives us only single bit of information (by the way, the device which does the actual comparing is, surprisingly enough, called a “comparator”). If we want more resolution (and we almost always do) and don’t want to play with Delta-Sigma or other related techniques, some ingenious way is to be found to increase the direct measurement resolution.

First approach is always a brute force one. We can add more voltage references, of values distributed across the useful range, and use an appropriate number of comparators to compare the input signal to all of those. Yes, it will take 1024 voltage references and 1024 comparators to achieve a measly 10 bit of resolution, and yes, such components do exist in the wild. They are exceptionally expensive, they consume a lot of power, and they are blazingly, up to tens of gigasamples per second, fast. Such ADCs are called “flash ADCs” and it’s worth mentioning those here because smaller offsprings of this ADC family (with 2 to 6 bits of resolution) serve as basic building blocks in other ADCs designs.

Now, when the brute force had taken us approximately nowhere, it’s time to resort to a somewhat more cunning technique called successive approximation (ADCs which employ this technique are called SAR, Successive Approximation Register ADCs).

The principle of SAR ADC operation is not utterly complicated. In its center lies a concept of a “SAR stage”. Each stage used a low resolution flash ADC to extract a fixed number of bits out of its input value, captured in the hold capacitor. These bits are captured for the user’s consumption, however, they are also used to synthesize a reference voltage using a built-in DAC, which voltage is then subtracted from the held input value. Remaining voltage difference is amplified by a fixed factor and provided at the SAR stage output.

Low resolution SAR stages can be imaginatively combined and reused to construct high resolution ADCs.

  1. The output of the SAR stage can be fed in round-robin fashion back to it’s input, to allow it several takes on the input signal value. The process is somewhat slow but requires very little hardware, and consequently, results in cheap and simple components.
  2. ADC can have multiple SAR stages chained together, so that output of one SAR stage is fed into an input of another in a pipelined fashion. The time to process a single sample will be as long as in p. 1, but multiple samples will be “in-flight” through the SAR chain, resulting in much higher throughput of the conversion channel. The majority of contemporary ADCs, apart from those succumbed to the DS creep, are implemented in this fashion.
  3. If there’s a need to convert multiple channels, a pipelined SAR can be coupled to an analog multiplexer to process those channels in parallel (at the expense of per-channel throughput, of course, and with considerable programmable flexibility, if not all available channels are, for some reason, needed).
  4. The reverse of p.3 is also possible: multiple pipelined SARs may be working on the same signal, sampling it at slightly different time moment. Such super-pipelined ADCs achieve throughputs exceeding those of flash ADCs and offer higher resolutions to boot, but, unfortunately, their still suffer from a largish conversion latency, which turns into a grave problem when high-bandwidth, rapidly changing signals are concerned.

Upon looking at what wonderful properties SAR ADCs have offer – low power consumption, simple structure, direct measurement of input value without non-obvious estimating filters, enormous achievable throughputs and seemingly arbitrary resolution, one may wonder: why would anybody bother with Delta-Sigma ADCs at all? And, as always in such cases, it’s mother Nature to blame.

It so happens, that each SAR stage produces a little bit of noise, which is added to its output. After sufficient number of stages, there will be no remnants of original signal left in the propagated input value, only noise. This problem is further exaggerated by the fact, that faster SAR stages tend to produce more noise, so that faster ADCs are limited to lower resolutions, everything else being the same.

Modern SAR ADCs typically can reach 16 bit resolutions at “ultrasound” (below 1 MSps) frequencies, while some particularly successful models being capable of 18 bits. In comparison, the almost entirely digital DS ADCs can easily utilize advances in logic circuit technologies and DSP algorithms to offer 24 or even 32 bits of per sample precision and gradually get fast enough to even displace pipelined SAR ADCs from high speed (> 1 MSps) applications.

One definitive edge SAR ADCs are expected to maintain over DS ones is their ability to “know” when exactly the sample was taken. More specifically, it is possible to make multiple SAR ADCs to sample their channels “simultaneously” within certain tolerance, while DS ADCs may find this apparently simple task problematic (DS loop filters have a rather complex phase response). This may matter quite a lot in applications like robotic hearing (beside many other) – when trying to locate a sound source by means of binaural audition even subtle phase differences can be of a big deal. As humans are binaural creatures as well, “simultaneity” of samples in different channels can be a neat gimmick in itself, when marketing of higher end equipment is concerned.

On a more personal, and some may think, delusional note, my soul, tired of all things digital, harbors a certain fondness to directly measuring SAR ADCs, as opposed to ungodly, value estimating Delta-Sigmas. High precision may be worth a lot, but knowledge that no evil DSP algorithm had tampered with my precious samples ahead of me is truly priceless.

Addendum: power consumption in ADCs of various technologies

Earlier in this article I promised to address the differences in power consumption required by various ADC technologies. To do a comparison, I compiled this short table of rather exotic components: 6 true differential channels, 16+ bits, differential input ADCs of sufficient speed. Those components were recently discussed in context of Six Pack project (hence, 6 channels):

Component Tech Sampling rate Resolution Power consumed
Cirus CS5366 Delta-Sigma 192 kSps 24 bits 680 mWM
TI ADS8365 SAR 250 kSps 16 bits 190 mW
Analog AD7609 Multiplexed SAR 200 kSps 18 bits 100 mW

Analog AD7609 is actually an 8 channel converter, thus it’s power consumption is a bit higher than “true” 6 channel converter would require. It is reasonable to expect a saving of 10mW for each unused channel (Analog Devices own estimate).

Further reading

One must not take blog posts from random people on the net too seriously. If topic is of interest, more serious sources must be consulted, and one such source is an excellent, not overly complicated, library of tutorials published by Maxim Integrated. The good starting place for exploration is their Data Conversion FAQ page.